IBM is making a major chip technology claim: a new nanostack transistor architecture that it describes as the “world’s first sub-1 nanometer chip technology” for AI data centers. The company says the design can integrate nearly 100 billion transistors on a chip the size of a human fingernail, nearly twice the transistor density of its previous generation.
The important point is that the claim does not mean every important chip feature is physically smaller than 1 nanometer. IBM is using the sub-1 nanometer language to describe the level of performance it expects from a new architecture, not a simple measurement of physical dimensions.
What IBM is actually claiming
IBM describes the new technology as a 0.7-nanometer node, which it calls the 7 angstrom node because 1 nanometer consists of 10 angstroms. That naming can sound straightforward, but modern chip node names no longer directly match the actual size of features on a chip.
That distinction matters. The source explains that reliably functional chips with transistors and other features smaller than 1 nanometer are impractical because of physical limitations. IBM’s argument is instead that its nanostack architecture can offer the kind of computing improvements that might be expected from a theoretical chip with physical features below that size.
Older chip generations developed in the 1970s and 1980s did have physical feature dimensions that matched the node name, such as chips made at the 180-nanometer node. That has not been true for decades, and it is not true for recent 3-nanometer or 2-nanometer process generations.
So the practical takeaway is simple: the 7 angstrom label is a technology-node claim. It is not a literal statement that the chip’s core physical structures are all 0.7 nanometers wide.
How nanostack transistors increase density
IBM’s approach is based on vertically stacking transistors in a staggered layout. By arranging more transistor structure within the same chip area, the company aims to push density higher without relying only on shrinking everything laterally.
The basic unit of IBM’s nanostack architecture consists of two transistors stacked and bonded together. Each transistor includes three nanosheets, and each nanosheet is individually 5 nanometers thick. IBM describes that thickness as equivalent to about 15 rows of silicon atoms. The source also notes a distance of about 9 nanometers separating each nanosheet.
This builds on IBM’s earlier nanosheet transistor work, which supported its 2-nanometer chip node introduced in 2021. According to IBM, that nanosheet architecture has become central to next-generation transistor scaling.
“Nanosheet has become the foundation of the next generation of transistor scaling,” said Huiming Bu, vice president of IBM Semiconductors Global R&D and IBM Research, during the media briefing. “Today, nanosheet is adopted by all leading foundries for most of the 3-nanometer chips and all of the 2-nanometer chips.”
The nanostack architecture is presented as the next step after nanosheet. Instead of merely refining the prior approach, IBM is trying to use vertical stacking to keep increasing transistor density when conventional scaling has become harder.
Why AI workloads are central to the pitch
IBM is tying the architecture directly to AI data centers. The company’s projections say nanostack chips could deliver 50 percent higher computing performance or 70 percent greater energy efficiency compared with IBM’s previous generation of 2-nanometer node chips.
Those two possibilities speak to the same pressure point. AI systems need large amounts of compute, but adding compute can also increase energy demand. IBM Research and IBM Fellow Jay Gambetta framed the advance as a way to make computing more powerful without a matching rise in energy use.
“It’s not just an incremental step, it’s a meaningful leap forward,” said Jay Gambetta, director of IBM Research and IBM Fellow.
Gambetta also described the technology as “pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy.”
The architecture also has a memory angle. IBM researchers showed how the nanostack architecture can provide 40 percent improvement in scaling for static random-access memory (SRAM) during the VLSI 2026 symposium. SRAM is important because it enables fast read and write operations, although the source describes it as energy-intensive.
The memory improvement comes from a staggered-channel design for SRAM bit cells. These memory storage units consist of six transistors. IBM says the design reduces overall cell height by 40 percent, allowing more SRAM to fit into the same chip space.
That could be significant for AI applications because SRAM scaling has fallen off sharply in recent chip generations. Gambetta explained that SRAM scaling improved just a few percent between the 3-nanometer chip generation and the 2-nanometer chip generation.
Commercial chips are still on the roadmap
IBM performs chip technology research, but it does not manufacture commercial chips that would directly ship into AI data centers or consumer devices. The path from research architecture to commercial hardware depends on manufacturing partners.
The source notes that IBM has partnered with semiconductor companies such as Rapidus in Japan to mass manufacture its previous generation of 2-nanometer node chips based on nanosheet architecture. IBM has also worked to commercialize related technology through another partnership with Samsung in South Korea.
Other companies have developed related approaches independently. Taiwan’s TSMC independently developed nanosheet transistors for its own proprietary 2-nanometer node technology.
For the new sub-1-nanometer node technology, IBM declined to name specific companies it may work with to commercialize it. Bu said commercial chips made at the sub-1-nanometer node and incorporating nanostack architecture could begin production as early as in the next five years and most likely within a decade.
“It will replace nanosheet as today’s mainstream in leading foundries, whether it’s CPUs or GPUs,” Bu said. “Within a decade, this will become another mainstream that we have invented and helped industry to transform.”
That timeline means IBM’s announcement is not about an immediate product launch. It is a roadmap signal: IBM is arguing that transistor scaling can continue through architecture changes, especially vertical stacking, even as simple shrink-based progress becomes more constrained.
The bottom line
IBM’s sub-1 nanometer chip claim is best understood as a performance-node milestone, not a literal statement about sub-1 nanometer physical features. The company’s nanostack architecture stacks and bonds transistors to increase density, with projected gains in compute performance, energy efficiency, and SRAM scaling.
If the technology reaches production on the timeline IBM describes, it could influence future CPUs, GPUs, and AI data center chips. For now, the key development is architectural: IBM is presenting nanostack as the successor to nanosheet for the next phase of transistor scaling.